1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same suited to a static random access memory (hereinafter, referred to as SRAM). In particular, the present invention relates to a semiconductor device and a method of fabricating the same for reducing the leak current of a field effect transistor (hereinafter, referred to as FET).
2. Description of the Related Art
For the sake of reduced cell areas, SRAM cells having such a structure that a single contact hole is shared among the gates of interconnected MOS transistors and the drain of another MOS transistor are now in use. FIG. 1 is a sectional view showing the structure of a conventional SRAM cell.
In this conventional SRAM cell, the drain of a first MOS transistor is connected with the gate of a second MOS transistor. A gate electrode 58 of the second MOS transistor is formed on a gate oxide film 57 on a silicon substrate 51. Side walls 59 are formed on the side surfaces of the gate electrode 58 and the gate oxide film 57. A low concentration diffusion layer 60a is formed at the surface of the silicon substrate 51 beneath the side wall 59 closer to the first MOS transistor. A high concentration diffusion layer 60b is formed outside the same. In addition, a silicide film 60c is formed on the high concentration diffusion layer 60b. Thereby is formed a drain region of the first MOS transistor.
An STI (Shallow Trench Isolation) oxide film 65 for element isolation is formed in the surface of the silicon substrate 51 beneath the side wall 59 farther from the first MOS transistor, so as to extend from outside the side wall 59 to under the gate oxide film 57. Moreover, a high concentration diffusion layer 60b and a silicide film 60c are formed in a region shown in FIG. 1 outside the oxide film 65 for element isolation, as in the drain region of the first MOS transistor. This portion makes part of a source region of the second MOS transistor (a high concentration region of an LDD (Lightly Doped Drain) structure). The gate electrode 58 makes a detour through a region not shown in FIG. 1 to a position across the source region from the portion shown in FIG. 1. A drain region (not shown) of the second MOS transistor is formed across the detouring portion of the gate electrode 58 from the source region.
Additionally, an interlayer insulation film 61 having a common contact hole 62a and a contact hole 62b is formed. The common contact hole 62a reaches the gate electrode 58 of the second MOS transistor and the drain-intended silicide film 60c of the first MOS transistor. The contact hole 62b reaches the source-intended silicide film 60c of the second MOS transistor. The common contact hole 62a is formed greater than the contact hole 62b by the size of the side wall 59. The common contact hole 62a and the contact hole 62b are filled with conductive films 63. Then, wiring layers 64 are formed on the conductive films 63, respectively. The wiring layers 64 consist of a lamination of, for example, a Ti film 64a, a TiN film 64b, an Al film 64c, a TiN film 64d, and a Ti film 64e. 
According to the conventional SRAM cell configured thus, the gate and the drain share the same contact hole. This allows a reduction in cell area as compared to the case where the contact holes are provided separately.
To fabricate an SRAM cell having the above-described structure, however, it is necessary to form the gate electrode 58, the side walls 59, the silicide films 60c and the like on the silicon substrate 51 before the interlayer insulation film 61 is formed all over and the common contact hole 62a and the contact hole 62b are made therein. This means a problem because at that occasion, a side wall 59 might be removed off together with the interlayer insulation film 61. FIG. 2 is a sectional view showing the state after the formation of the common contact hole 62a and the contact hole 62b. As shown in FIG. 2, if the side wall 59 is removed, there can occur a leak current to the silicon substrate 51. The decrease of the side wall 59 may be suppressed by controlling the etching selectivity between the interlayer insulation film 61 and the side wall 59, whereas not as much as the leak is prevented.
As mentioned above, the common contact hole 62a is greater than the contact hole 62b by the size of the side wall 59. Therefore, the reduction in cell area is hardly adequate. Moreover, due to the different sizes of the contact holes, a resist film to be used as a mask for opening these holes is difficult to pattern.
Furthermore, there has been proposed a trench gate type MOSFET in which, for the sake of reduced switching delay time, a gate oxide film is formed along the bottom and sides of a trench, and a gate electrode shaped to increase in size upward is formed thereon (Japanese Patent Laid-Open Publication No. Hei 7-38095). Even in this case, the formation of a common contact hole inevitably exposes and etches the side wall.